The present invention relates to a radio paging receiver and, more particularly, to a circuit for minimizing a loss of data and for producing effective battery saving signals for use in a radio paging receiver.
Generally, the paging receiver which introduces a battery saving system is structured as shown in FIG. 1. Referring to operation of the prior art system, radio frequency which is sent out from a sending station is applied to a radio frequency (RF) section 11 of a radio paging receiver through an antenna 10. By means of the RF section 11, the RF signals received through the antenna 10 is amplified and the frequency of the RF signal is converted by a general double-super-heterodyne or homodyne receiving system. Thereafter the resultant signals are filtered and demodulated by a filter and a demodulator. Waveform shaper 12 converts the demodulated signals outputted from the RF section 11 into a digital signal by means of a filter and comparator because the demodulated signal is very weak and has high frequency noise therewith. Then, data processor 13 analyzes output of the waveform shaper 12 and controls various functions of the radio paging receiver.
In usual, the data processor 13 produces battery-saving-on (BSON) signals. Such BSON signals drive a switching circuit 14 thereby to control the supply of power 15 which is applied to the RF section 11 and to the waveform shaper 12 by way of the switching circuit 14.
Such a known method is generally employed in a compact battery-using receivers like a radio paging receiver in order to save the power consumption. The data processor 13 generates alternately battery-saving-on (logic high) and battery-saving-off (logic low) signals with regular intervals. If a preamble is received when battery-saving-on signal is generated, the BSON (battery-saving-on) signal is kept on being generated. While the switching circuit 14 is turned "on" the power 15 is supplied to the RF section 11 and the waveform shaper 12. The data processor 13 is thereby enabled to receive data.
Regarding now a general waveform shaping process in reference to FIG. 2, the demodulated signal which is outputted from the RF section 11 is cleared of high frequency noise by means of a filter 21. The filter 21 is comprised of a low pass filter to remove high frequency noise, the low pass filter having passive elements such as resistance and capacitance. The demodulated signals which get through the filter 21 are converted into digital signals by means of the comparator 24 and thereafter applied to the data processor 13. In other words, the demodulated signals are applied to the non-inverting terminal of comparator 24 through resistance 23 and a part of the demodulated signals are integrated by integrator comprised of resistor 22 and capacitor 25 to be applied to the inverting terminal of comparator 24. Thus, the comparator 24 converts the demodulated signals into digital signals by comparing the voltage level of the integrated signals which are applied to the inverting terminal as reference voltage with the voltage level of demodulated signals which are applied to the non-inverting terminal in form of analog signal.
The concrete operational waveforms of the waveform shaper 12 is illustrated in FIG. 3. The moment BSON signal as shown at 3b is generated by the data processor 13, the power 15 is supplied to the RF section 11 and the waveform shaper 12, and the filter 21 then generates a demodulated signal which is filtered like 3c. Then, output of the filter 21 is applied to the non-inverting terminal of the comparator 24 like 3d through the resistor 23. The output of the filter 21 is also applied to the inverting terminal of comparator 24 like 3e after being integrated by the integrator comprised of the resistor 22 and capacitor 25.
However, the input voltage applied to the inverting terminal as a reference voltage of the comparator 24 reaches to the reference voltage V2 only when time TL passes by the time constant of the resistor 22 and capacitor 25, as shown at 3e after the power 15 is applied. Consequently, there arises a problem that the radio paging receiver loses input data as shown in during the time TL among the received data of 3a.
To solve such a problem as stated above, a method disclosed in the U.S. Pat. No. 4,479,261 includes a first switching circuit and a second switching circuit. The battery is supplied to the waveform shaper 12 through the first switching circuit and to the RF section 11 through the second switching circuit. In the U.S. patent, the delay time TL is determined in advance by the time constant of capacitor 25 and the resistance 22, which generates the reference voltage which is applied to the inverting terminal of the comparator 24. When the BSON signal is generated to receive data, the power 15 is supplied to the waveform shaper 12 by driving the first switching circuit so as to make compensation for the delay time TL first and the power 15 is supplied to the RF section 11 by driving the second switching circuit after the time TL is delayed.
However, such a method requires more power supply to the waveform shaper 12 during the TL period every time the BSON signal is generated in order to ascertain if data is received, thereby causing power consumption to rise in a compact radio paging receiver.